The present disclosure relates to a multi-layer ceramic electronic component such as a multi-layer ceramic capacitor.
Typically, a multi-layer ceramic capacitor is produced as follows. First, unsintered ceramic green sheets on which a plurality of internal electrode patterns are respectively formed are laminated. Subsequently, the laminate of the ceramic green sheets is cut at predetermined positions, and an unsintered ceramic body in which side margins and end margins are formed in the periphery of the internal electrodes is produced. The ceramic body is sintered, and external electrodes are formed on the surface of the ceramic body, so that a multi-layer ceramic capacitor is produced.
In the production processes described above, the deviation of lamination at the time of lamination of the ceramic green sheets or the deviation of cut positions at the time of cutting may occur. The occurrence of such deviation causes the positions of the internal electrodes to be deviated from design positions and makes it difficult to sufficiently ensure insulation properties and environment resistance of the internal electrodes.
There is known a method of determining the lamination accuracy of ceramic green sheets or determining the correctness of a cut position in a laminate on the basis of the shapes of the internal electrodes exposed at the surface of the ceramic body.
For example, Japanese Patent Application Laid-open No. Hei 10-275736 discloses a method of producing a laminate substrate on which an internal electrode pattern including a partial blank is formed, and determining the correctness of a lamination position of the laminate substrate on the basis of the presence/absence of a non-exposed portion corresponding to the partial blank of the internal electrode on an end surface of the laminate.
Further, Japanese Patent Application Laid-open No. Hei 5-226178 discloses a multi-layer ceramic capacitor in which a marker for confirming a laminated state is formed in a side margin between an internal electrode and the side surface of a chip, in which the lamination accuracy is confirmed depending on a state where the marker is exposed at an end surface at which the internal electrodes are exposed.